The effects of etching and deposition on the performance and stress evolution of open through silicon vias

In order to embed more functionality and performance into the same design space, 3D IC integration technology is one of the routes towards further miniaturization of ICs and consequently, printed circuit boards. 3D TSV (through silicon via) stacking of wafers or dies requires die-to-die interconnections to conduct electricity and heat. Typically micro bump contacts with solder (e.g. AgSn) and Cu TSV are used. Process and quality control of these advanced packaging processes and the resulting 3D products is challenging, but a necessity to avoid costly device failures due to packaging faults. We employed a lab-source microfocus X-ray computed tomography system to demonstrate the capability of non-destructive detection and characterization of such die-to-die interconnections with features in the micron range. Structural characteristics and flaws, such as electrical shorts, voids, filling faults, or composition features could be reliably identified. We demonstrate the use of submicron X-ray computed tomography for non-destructive process development, process monitoring and failure analysis in 3D TSVs stacks on a packaged test chip with dimensions 10 × 10 × 0.9 mm3 that consists of six chip layers with TSVs and microbumps as well as AgSn solder.